Re: [Yaffs] Bad eraseblocks and NAND / ECC layouts

> -----Original Message-----
> From: yaffs-bounces@lists.aleph1.co.uk [mailto:yaffs-
> bounces@lists.aleph1.co.uk] On Behalf Of Rong Shen
> Sent: Friday, 29 May 2009 11:57 AM
> To: Noah Fontes
> Cc: yaffs@lists.aleph1.co.uk
> Subject: Re: [Yaffs] Bad eraseblocks and NAND / ECC layouts
>
...
> 1. completely wipe the flash, data and spare area
> 2. (optional) a read scan of the chip to identify all the blocks
> containing one or more 0s (or ECC errors), and mark them as bad
> 3. write certain patterns to the flash (e.g. 0x00, 0xff, 0x5a, 0xa5
> for byte orientated chip, one pattern for each round), and read back,
> if there's any mismatch or ECC errors for any block, mark it as bad.
> 4. erase the remaining good blocks to be ready for use.
>

This would miss certain classes of error - such as charge leakage (e.g.
the cells will erase or set themselves over a day/week/month/year).

http://lists.openmoko.org/pipermail/community/2007-July/008471.html

James