[Yaffs] YAFFS support for 16bit NAND flash

[Charles Manning]

On Thursday 18 November 2004 22:27, adam.charrett@philips.com wrote:
> I'm currently try to evaluate whether to use YAFFS for a project on one=
 of
> our chips and having looked at the spec am unsure as to whether YAFFS
> could/does support 16Bit NAND flash.
> The only difference between 8Bit NAND flash adn 16bit as far as YAFFS i=
s
> concerned would be where the Bad Block information is stored and the fa=
ct
> that a 2byte word is used instead of 1 byte.
>
> Has any one used YAFFS with a 16bit device?
>
> Are there any plans to support 16bit devices?
>
> Many thanks
>
> Adam

Hi all,=20

Sorry to be so late to the party (was away for a short hike last week).

YAFFS will work fine with a 16-bit NAND device (ie. one with a 16-bit bus=
 but=20
512byte pages/32 pages per block). These devices use 8 bits for accessing=
 the=20
command registers and use 16-bits for pumping the data.=20

As Wookey has noted, you need to check the rewrite-happiness because YAFF=
S1=20
needs to be able to write delete flags to the spare when a page gets=20
discarded. That, however, is independent of the 16-bit bus issue. YAFFS2 =
has=20
no such constraint.

The bad block marking is no problem at all since YAFFS always reads/write=
s=20
either the data (512bytes) or spare (16 bytes) as a single operation. The=
re=20
is no access where YAFFS reads only one byte at a time.

Where theses devices can really pay off is that the wider bus width can m=
ove=20
the data faster (x16 cycles rather than x8 cycles). Futher, with devices =
like=20
an ARM you can use ldmxx/stmxx to get way better performance.

-- Charles