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f579840)
In the past only non-aligned or inband-tags writes were written
into the internal cache. However the cache has some benefits
with certain write patterns, so the default has been changed to
always write into the cache.
A control parameter has been added to bypass the cache for aligned writes.
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
}
if (n_copy != dev->data_bytes_per_chunk ||
}
if (n_copy != dev->data_bytes_per_chunk ||
+ !dev->param.cache_bypass_aligned ||
dev->param.inband_tags) {
/* An incomplete start or end chunk (or maybe both
* start and end chunk), or we're using inband tags,
dev->param.inband_tags) {
/* An incomplete start or end chunk (or maybe both
* start and end chunk), or we're using inband tags,
+ * or we're forcing writes through the cache,
* so we want to use the cache buffers.
*/
if (dev->param.n_caches > 0) {
* so we want to use the cache buffers.
*/
if (dev->param.n_caches > 0) {
/*
* Entry parameters set up way early. Yaffs sets up the rest.
* The structure should be zeroed out before use so that unused
/*
* Entry parameters set up way early. Yaffs sets up the rest.
* The structure should be zeroed out before use so that unused
- * and defualt values are zero.
+ * and default values are zero.
*/
int inband_tags; /* Use unband tags */
*/
int inband_tags; /* Use unband tags */
int n_caches; /* If <= 0, then short op caching is disabled,
* else the number of short op caches.
*/
int n_caches; /* If <= 0, then short op caching is disabled,
* else the number of short op caches.
*/
+ int cache_bypass_aligned; /* If non-zero then bypass the cache for
+ * aligned writes.
+ */
+
int use_nand_ecc; /* Flag to decide whether or not to use
* NAND driver ECC on data (yaffs1) */
int tags_9bytes; /* Use 9 byte tags */
int use_nand_ecc; /* Flag to decide whether or not to use
* NAND driver ECC on data (yaffs1) */
int tags_9bytes; /* Use 9 byte tags */